In a test system there are many sources of timing errors. One such error that can not normally be corrected for in timing calibration is the mismatch in impedance between the output impedance of the device under test (DUT) and impedance of the signal path from the DUT to the receiver. Typically, the distance between the DUT and receiver is anywhere from 6 to 18 inches. If the output impedance of the DUT is greater than the signal path impedance, the output pulse of the DUT will appear rolled-off. The signal is rolled-off due to reflections caused by mismatch in impedance. Since a signal travels approximately 12 inches in 1.8 ns, the round trip delay can introduce a maximum error from 1.8 ns to 5.4 ns to the receiver.
By reducing the distance to 2 inches or less, the maximum error introduced about be 600 ps. If the output impedance of the DUT is smaller than the impedance of the signal path, a ringing or oscillation will occur. This oscillation will trip the receiver multiple times, making the functional testing of the DUT difficult to be performed at the device specification. The cycle of oscillation is dependent on the distance between the DUT and receiver. Depending on the magnitude of the impedance mismatch, it can take up to 4 cycles for the oscillation to dampen out. For distances of 6 to 18 inches, the time for damping is from 7.2 ns to 21 ns. For 2 inches or less, this time is 2.4 ns or less.
Relays in the high speed paths of testers also introduce insertion loss errors. Relays exhibit 0.3 db loss at 200 mhz. This relates to approximately 4% signal degradation.
Relays are also inherently unreliable with a typical life time of 10 exp8 switching cycles.
By using FETS to replace relays in the critical device signal paths, a short distance of two (2) inches or less (based on a 256 pin test head) can be achieved to the DUT. Relays can also be eliminated from the high speed and high usage paths to increase signal integrity and reliability.
There are three (3) major reasons FETs have not been used instead of relays in the past; 1) the leakage current of silicon FETs introduce errors when the DUT bias currents (IIN) are measured. This leakage is very difficult to calibrate out of the actual bias current of the DUT. The leakage also increases as the size of the FET increases to reduce the "ON" resistance of the FET. Low "ON" resistances of the FET are necessary to force high current for DUT voltage output measurements (VOL, VOH); 2) The lumped capacitance of FETs can also introduce insertion loss errors and limit frequency response of the DUT and tester electronics. The lumped capacitance of a FET increases as the size of the FET increases to reduce the "ON" resistance. Low "ON" resistance is also necessary to improve frequency response. 3) GaAs MESFETs have a much lower capacitance than silicon FETs, but the leakage current is much higher.